T3ISC builds ternary silicon — chips that think in three states instead of two — purpose-built for the efficient-AI models the industry is already racing toward. Same accuracy. A twelfth of the energy. Printed on the standard binary CMOS your foundry runs today.
Everyone is staring at AI — so are we. But the same silicon carries a measured win for the computing everyone else has forgotten, and a silicon-economics story that makes the margin.
The anchor. The fastest-growing electricity bill in computing, cut by ~91% — same model, same accuracy, a twelfth of the energy.
measured · 11.6×, shown roundedWhile the world optimises AI, the rest of the estate still burns power. Across the integrated system, ordinary workloads get a measured 1.3× efficiency win — at CPU performance parity with production server-class cores. Real, bounded, and honest.
measured · silicon gradeThe same AI throughput from 2–3× fewer square millimetres of die. Smaller die, more chips per wafer, structurally lower cost per token — 10×+ at the hardware level. Efficiency sells the product; silicon economics make the margin.
engineering modelInside every AI chip, the arithmetic is nearly free. The energy bill comes from moving data — fetching billions of weights from memory, over and over, for every single token. Data centres are now power-capped, not silicon-capped. The winner of the AI era is whoever moves the least data.
AI inference is the largest and fastest-growing line item in computing — and the grid, not the silicon, is now the limit on growth.
Serving a large model means streaming its weights through the chip for every answer. Shrink the weights, and you shrink the entire energy bill.
FP16 → FP8 → FP4 — every leading chipmaker is racing to fewer bits per weight. Ternary is the floor of that ladder. We build the silicon that lives there.
Energy-per-operation versus energy-per-off-chip-fetch ratios are well established in published silicon literature; the figure shown is an order-of-magnitude illustration, not a T3ISC-specific claim.
Modern efficient-AI models (the BitNet class) need each weight to say only three things: negative, zero, or positive. Storing that in 16-bit floating point wastes ~90% of every byte. A ternary digit — a trit — stores it natively. Same answers, a fraction of the data.
The value "−1", as silicon actually stores it:
Information theory: one trit carries log₂3 ≈ 1.585 bits. Ternary-weight models are published, peer-reviewed art (BitNet b1.58); T3ISC builds the silicon that runs them natively instead of emulating them on binary maths units.
Bits stored per weight. The whole industry is climbing down. We're waiting at the bottom.
Below ternary, model accuracy collapses — published research shows three levels is the matched representation for AI weights. This is the end-state of the precision race, and it's defensible: you can't go lower.
Weight trits stream into the compute core — +1 passes straight through, −1 flips for free, 0 is skipped entirely — and the answer accumulates. Drag to orbit. Tap a floating trit. Pulse a batch.
Two identical AI workloads, side by side — conventional binary versus T3ISC ternary. Both produce the same answer. Watch the energy meters.
Paced from the measured whole-system energy-per-token advantage (≈12× vs FP16 — 11.6× measured, shown rounded — switching-activity measurement on industry-standard silicon tooling) and the measured 4–12× performance-per-watt composite range. Ratios, not mechanism — how the silicon does this is the patented part.
The memory wall is paid in bytes moved. Binary streams 16 bits per weight; ternary streams a trit. Watch the pipes — same result out, 8× less data through.
Pick a serving workload. Both halls below have the same floor area and the same throughput — the difference is how much of it ternary silicon actually needs to power. The dark cells are racks you never build.
Illustrative model: equal token throughput; consolidation from the measured ≈12× energy-per-token ratio (11.6× measured, applied conservatively as 10× rack consolidation); 120 kW per conventional accelerator rack; PUE 1.2; £0.10/kWh electricity only; grid intensity 0.35 kgCO₂/kWh. Total cost-of-ownership savings are larger still — cooling plant, floor space and hardware all shrink with the racks. The ratio is the product; the absolute figures are arithmetic — substitute your own assumptions and the percentages hold.
AI inference is the anchor — but the same silicon reaches the structured-data workloads that dominate the modern data centre. Where the data has structure, the advantage applies. Where it doesn't, we coexist with conventional hosts — and say so.
The flagship: ≈12× measured energy per token vs FP16, accuracy preserved. The fastest-growing electricity bill in computing, cut by ~91%.
measuredCore video-processing blocks validated bit-exact at silicon grade. Streaming, transcoding and media pipelines ride the same efficiency substrate as AI.
validated bit-exactColumnar scans and streaming analytics map naturally onto the architecture — component-level measurements on these access patterns reach an order of magnitude lower power against production reference designs.
measured · component levelNeural rendering measured at 2.5× performance-per-watt against published figures for a flagship gaming GPU — the advantage extends into graphics, gaming and visual computing.
measured proxyThe same architecture scales down to battery budgets — on-device AI, wearables and ambient compute, where every milliwatt is product-defining.
architecture validatedPlain server logic doesn't carry the same structure, so we don't claim 12× there — we measure a 1.3× whole-system win, at CPU performance parity. T3ISC coexists with conventional hosts and wins where the advantage is decisive — the Apple-Silicon playbook. Investors hear claims; we publish boundaries.
honest boundaryWorkload coverage figures are per-class measurements at the stated grades, not a uniform system-wide multiple. The data-centre savings modelled on this page are anchored to AI inference — the largest and fastest-growing slice — with the structured-data classes above extending the addressable share.
Deep-tech hardware fails on optimistic numbers. Ours are produced the opposite way: every figure is measured on industry-standard silicon tooling, then attacked by an independent adversarial verification pass before it is allowed into the record. Claims that didn't survive were retired — publicly, in our own audit trail.
Whole-system measurement — full design, real switching activity, end to end on industry-standard silicon tooling. A 91% reduction in the energy each answer costs. The "12×" on this page is this figure, rounded.
measured · silicon-gradeThe honest composite range — architecture × ternary numerics × system integration, folded conservatively with every overlap removed. We publish the range, not the cherry-pick.
measured compositeMeasured across the integrated system at silicon grade on ordinary, non-AI workloads — with CPU performance at parity with production server-class cores. The efficiency is additive, not traded for speed.
measured · silicon-gradeA 2-billion-parameter ternary model run through the full architecture produces answers within 1.4% perplexity of full precision — bit-exact functional correctness across 1,024 of 1,024 verification vectors.
measured · end-to-endNeural rendering measured on real hardware, compared against published figures for a current flagship GPU — evidence the advantage extends beyond chat into graphics, media and the wider efficient-AI stack.
measured proxy · real hardwareModelled die area for the server-class part. Fewer square millimetres per token means more chips per wafer — the margin advantage is built in at manufacture, before the energy savings even start.
engineering modelNew chips die when nothing runs on them. Real programs compile and run on our architecture today, verified bit-for-bit against a standard reference — the "Itanium risk", retired before tape-out.
verified bit-exactThis is not a bet on a new material, a new transistor, or a new fab. T3ISC's ternary architecture is implemented entirely in standard binary CMOS — the same process, the same transistors, the same foundries manufacturing today's chips.
Manufacturable on production nodes at existing foundries. No new equipment, no new materials, no process risk added to the venture.
The architecture has been carried through synthesis, place-and-route and energy measurement on the same class of tooling production silicon teams use.
Ternary-weight models are published, open art with frontier-lab momentum behind them. The models exist; what's missing is silicon that runs them natively. That's us.
The architecture speaks standard interfaces and coexists with conventional hosts — adopting it doesn't mean replacing the data centre, just shrinking it.
Engineers have known for nearly two centuries that three states beat two on efficiency. What was always missing is a way to build it without exotic devices. That's the part we solved — and patented.
Thomas Fowler, a self-taught English inventor, builds a working calculating machine in wood — using balanced ternary because it needed far fewer parts than decimal or binary designs of the day.
Nikolay Brusentsov's Setun at Moscow State University runs on balanced ternary — and proves cheaper and more reliable than binary contemporaries. Roughly fifty are built before the project is shut down for standardisation, not for engineering reasons.
Donald Knuth, in The Art of Computer Programming, singles out balanced ternary for its elegance — flagging that hardware might one day return to it. For decades, binary fab economics kept that day from coming.
Microsoft Research shows that large language models run on ternary weights {−1, 0, +1} with accuracy matching full precision — at 1.58 bits per weight. The workload the world most wants to run cheaply turns out to be natively ternary.
T3ISC closes the 186-year gap: a ternary architecture implemented entirely on standard binary CMOS — no exotic devices, no new fabs. Patents filed. The precision ladder ends here, and we own the floor.
served market by 2032 — AI inference across cloud and edge data centres through embedded, plus the cross-domain workloads (media, analytics, secure compute) where the same advantage applies.
Dominate the workloads where a purpose-built advantage is decisive, rather than competing everywhere. Specialist platforms win categories.
The industry is moving to radically more efficient models — but is still serving them on general-purpose silicon designed for a previous era. Purpose-built silicon captures an order-of-magnitude gap incumbents cannot close by tuning.
Patent-protected architecture (priority window open) · a working end-to-end software stack competitors consistently underestimate · and a verification discipline that survives due diligence.
Full system, silicon-grade evidence on every load-bearing component.
Adversarial verification across the measured claim set. Zero unverified figures.
Real programs compile and run, bit-exact against reference. Itanium risk retired.
First applications filed; further filings inside the international priority window.
Foundry partnership and tape-out path, funded by this raise.
The deepest technical risks — architecture, efficiency, software — are already retired and independently verified. Capital now converts directly into the tape-out path, on the Apple-Silicon precedent, into a market being rebuilt around energy.